Default MAKE macros
-------------------
MAKE contains several default macros you can use in your makefiles.
The following table lists the macro definition and what it expands to
in explicit and implicit rules.

Macro   Expands in implicit:    Expands in explicit:    Example
-----   --------------------    --------------------    -------
$*      path\dependent file     path\target file        C:\PROJ\MYTARGET

$<      path\dependent file+ext path\target file+ext    C:\PROJ\MYTARGET.OBJ

$:      path for dependents     path for target         C:\PROJ

$.      dependent file+ext      target file + ext       MYSOURCE.C

$&      dependent file          target file             MYSOURCE

$@      path\target file+ext    path\target file+ext    C:\PROJ\MYSOURCE.C

$**     path\dependent file+ext all dependents file+ext F1.CPP F2.CPP F3.CPP

$?      path\dependent file+ext old dependents          FILE1.CPP


Macro           Expands to:     Comment
-----           -----------     -------
__MSDOS__       1               If running under DOS.

__MAKE__        0x0370          MAKE's hex version number.

MAKE            make            MAKE's executable file name.

MAKEFLAGS       options         The options typed at the
                                command line.

MAKEDIR         directory       Directory where MAKE.EXE is
                                located.